In a double diffused MOS (DMOS) FET employing a silicon carbide (SiC) semiconductor substrate, an n−-type SiC semiconductor epitaxial layer is provided on a surface of an n+-type SiC semiconductor substrate. A p-type impurity region is provided in a surface portion of the n−-type SiC semiconductor epitaxial layer, and an n+-type impurity region having an annular shape as seen in plan is provided in the p-type impurity region.
FIG. 7 is a diagram illustrating an impurity profile in the p-type impurity region in the prior-art double diffused MOSFET. In the prior-art double diffused MOSFET, the p-type impurity region has a so-called box profile. That is, the profile in the p-type impurity region in the prior-art double diffused MOSFET is controlled as having a generally uniform impurity concentration irrespective of the depth from the surface of the p-type impurity region.
The p-type impurity region having such a box profile is formed by implanting a p-type impurity into the surface portion of the n−-type SiC semiconductor epitaxial layer by multi-step ion implantation. Ion implantation performed with constant implantation energy (single-step ion implantation) provides a depthwise impurity distribution approximate to the Gaussian distribution (as indicated by two-dot-and-dash lines in FIG. 7). Therefore, by performing ion implantation with three different levels of implantation energy (three-step ion implantation), for example, a near surface of the p-type impurity region and the deepest portion of the p-type impurity region (on a boundary between the p-type impurity region and the n−-type SiC semiconductor epitaxial layer) are allowed to have substantially the same impurity concentration.
When the deep portion of the p-type impurity region has a lower impurity concentration, a depletion layer is liable to spread into the p-type impurity region from the boundary between the p-type impurity region and the n−-type SiC semiconductor epitaxial layer, so that punch-through is liable to occur. Therefore, a breakdown voltage of the prior-art double diffused MOSFET is sufficiently increased by setting the impurity concentration of the p-type impurity region at a high level on the order of 1017 to 1018/cm3. However, where the p-type impurity region has a high impurity concentration, carriers moving in a channel region are liable to be scattered. This disadvantageously reduces the carrier mobility in the channel (increases the ON resistance).